(1) Field of the Invention
The present invention relates to the manufacture of ultra large scale (ULSI) semiconductor chips in general, and in particular, to an integrated method of forming interconnect layers using a dual-layered top surface imaging (TSI) process as an improvement for dual damascene metal wiring technology.
(2) Description of the Related Art
The significance of the use of the presently disclosed dual layer photoresist process in the ULSI technology becomes more apparent when one considers the challenges associated with the forming of interconnections in the high performance chips of related art.
In order to affect more readily the migration of the very large scale integrated (VLSI) technology towards the ULSI technology for higher speed and performance of computers, the semiconductor industry has been providing in rapid succession new techniques and technologies for manufacturing very tightly packed semiconductor chips. As is well known by those versed in the art, closer proximity of devices in a tightly packed chip not only provides higher propagation speed of electrical signals by the sheer reduction in the traveled distance between the devices, but also by the reduced impedance encountered in the shortened medium through which the signals travel. On the other hand, tightly packed, ultra large scale integration can be achieved with only ultra small devices and interconnections.
The interconnections in turn must be formed in a such a manner so as to minimize the increased resistance to signal propagation through the reduced cross-section of the wiring metal stripes. It is especially important to avoid mating contacts and favor solid connections where possible.
A semiconductor chip normally contains one or more metal wiring layers that are separated from each other by an insulating layer and are further separated by still another insulating layer from the devices that are formed near the surface of the semiconductor that forms the base of the chip. The wiring stripes are connected to each other and to the devices at the appropriate places by means of holes that are filled with metal through the insulating layers. In prior art, there are many different methods of forming metal lines and interconnections between them. The holes that connect the metal lines to each other through the insulating layer are called via holes, while the holes that reach the underlying devices through its insulating layer are called contact holes. Typically, the holes are etched into an insulating layer after the latter has been deposited on the semiconductor substrate on which the chips are fabricated. It is common practice to next blanket deposit metal on the insulating layer thereby filling the holes and then forming the metal lines by etching through a patterned photo resist formed on the metal layer. For the first metal layer, electrical contact is made with the underlying devices through contact holes, or windows, that allow the metal to descend through the dielectric insulator to the devices. For the second and subsequent wiring layers, the process is repeated and the contact between the metal layers is made through via holes that allow the metal to descend to the lower metal layer(s). It is also common practice to fill the holes separately with metal to form metal plugs first, planarize or smoothen them next with respect to the surface of the insulating layer and then deposit metal layer to make contact with the via plugs and then subtractively etch as before to form the required "personalized" wiring layer.
To provide robust contact area at the junction where the metal lines contact the devices or the via plugs in the case of multilayer wiring, it is usually necessary to increase the dimensions of the various features in the metal line and the holes to compensate for overlay errors and process bias inherent in lithographic process. This increase in the size of the design ground rules results in a significant loss in circuit layout density. Furthermore, there is considerable development effort expended on photolithographic equipment and processes to make improvement in overlay error and process tolerances. To minimize the chip area devoted to overlay tolerance and lithography costs, several "self-aligned" processes have been developed by workers in the field.
There are also other problems associated with forming contacts between metal layers in a substrate. Where contact windows are etched into a dielectric layer, the sides of the contact windows must be sloped to guarantee good continuity of the metal layer as it descends into the contact window. The steeper the slope, the more likely it is the metallurgy will have breaks at the edges of the contact windows. However, the use of a gradually sloped sidewall to guarantee metal line continuity takes up valuable chip area and prevents contact windows from being packed as closely as desired. In addition, the use of contact windows creates an irregular and nonplanar surface which makes it difficult to fabricate the subsequent interconnecting layers as shown in FIG. 1.
The structure shown in FIG. 1 is a typical example of a semiconductor substrate fabricated using prior art techniques. After having defined device regions represented by reference (11) on substrate (10), a first insulating layer (12) is formed and patterned thereon. First level metal layer (13) is next deposited to make contact with region (11) through contact window (14). Similarly, the second level metal layer (16) makes contact with metal layer (13) through via hole (17) patterned in second insulating layer (15). The structure is passivated with a third insulating layer (18). Although the structure depicted in FIG. 1 is not to scale, it exemplifies a very irregular surface which creates reliability problems. One such problem is the potential short at location (S) between the first and second levels of metal layers, due to the thinning of the insulating layer therebetween, and still another one is the risk of a potential open circuit at locations (O, due to the thinning of the metal layer at that location.
One solution that is found in prior art in addressing the problems cited above is the so called Dual Damascene process. In its simplest form, this process starts with an insulating layer which is first formed on a substrate and then planarized. Then horizontal trenches and vertical holes are etched into the insulating layer corresponding, respectively, to the required metal line pattern and hole locations that will descend down through the insulating layer to the underlying features, that is, to device regions if through the first insulating layer, or to the next metal layer down if through an upper insulating layer in the substrate structure. Metal is next deposited over the substrate thereby filling the trenches and the holes, and hence forming metal lines and the interconnect holes simultaneously. As a final step, the resulting surface is planarized using the well-known chemical-mechanical polish (CMP), and readied to accept another dual damascene structure, that is, integrally inlaid wiring both in the horizontal trenches and vertical holes, hence the duality of the process.
A dual damascene structure before and after CMP is shown in FIGS. 2a and FIG. 2b. Two photolithographic processes and two insulator layers separated by an etch-stop layer are employed to achieve the shown structure as follows: a starting planarized surface (30) is provided with patterned first level metal (31). A first layer of insulator (32) is deposited over a fist level of patterned metal to which contacts are to be selectively established. The first layer is planarized and then covered by an etch-stop material (33). Contact holes are defined in the etch-stop material by a first photolithography at locations where vertical plug interconnects are required. The thickness of the first insulator layer (32) is made equal to the desired plug height. The first insulator layer is not etched at this time. Next, a second insulator layer (34), having a thickness equal to the thickness of the second level of patterned metal of the mullet-level structure, is deposited over the etch-stop material (33). The second insulator layer (34), in turn, is etched by second photolithography down to the etch-stop material (33) to define desired wiring channels (40), some of which will be in alignment with the previously formed contact hole (41) in the etch-stop material. In those locations where the contact holes are exposed, the etching is continued into the first insulator layer to uncover the underlying first level of patterned metal. The horizontal channels and vertical holes etched into the second and first insulator layers are next overfilled with metal (35). As a final step, excess metal (35) on top of the second insulator layer (34) but not in the channels (40) or holes (41) is removed by etching or chemical-mechanical polishing, as shown in FIG. 2b.
It will be appreciated by those skilled in the art that the dual damascene process alleviates the problem of registration of holes with metal lines, and the concomitant issue of excessive overlay tolerances. At the same time, wiring can be kept to the minimum ground rules tolerances and also problems associated with the thinning of insulator and/or metal around sloped holes can be circumvented. However, it is also evident that the process is complicated, especially in the area where two photolithographic steps must be performed to form the vertical holes. Here, the hole pattern must first be defined lithographically after the etch-stop has been formed, and also later when the hole is etched lithographically. Furthermore, the etch-stop, which is usually an oxide, has to be formed as an intermediate layer subject to a baking process performed at a high temperature. Facilities for etching the oxide film are additionally needed. The addition of this complicated processing results in lower productivity, increased density, and increased cost.
Nevertheless, in prior art, dual damascene process has been used to advantage. For example, Shoda discloses in U.S. Pat. No. 5,529,953 a method of manufacturing a stud (vertical metal plug) and (horizontal) interconnect in a dual damascene structure using selective deposition where the selective deposition is accomplished through repeated application of masks and photolithographic processes. Similarly, Zheng in U.S. Pat. No. 5,602,053 discloses a dual damascene antifuse structure where sandwiched layers are formed. In another approach, recognizing the multiplicity of mask patterning steps in dual damascene process, Avanzino in U.S. Pat. No. 5,614,765 teaches the use of one mask pattern for the formation of both the conductive lines and the vias simultaneously.
It is advantageous, therefore, to be able to replace the complicated portions of dual damascene process with new methods, and apply the process more effectively to the manufacture of semiconductor substrates and chips. It is disclosed in this present invention that in fact a modified and improved silylation process can be advantageously incorporated to improve the present state of the art of dual damascene process.